Why AI agents struggle with chip design (RTL) debugging, and what helps

A case study on a reintroduced VeeR EL2 forwarding bug in Caliptra found that Claude Code located the faulty RTL line within five minutes but spent most of its time reproducing the bug, because internal signals are invisible without waveform recording and simulations are long enough that the agent guesses when they finish. Running the same agent with Booley, an open-source RTL agent harness, cut mean time to a verified fix from 55.8 to 21.3 minutes across ten paired trials, with the largest hardware-specific gain coming from recording a waveform once and querying it instead of rebuilding to add prints. The author notes this is a single-bug case study, not a benchmark, and that the harness did not supply the microarchitectural reasoning needed to make the bug appear.